1. Field of the Invention
The present invention relates generally to an embedded chip package structure, more particularly to an embedded chip package structure wherein an embedded semiconductor chip can be electrically connected to external circuitry directly through the package structure.
2. Description of Related Art
With rapid development of semiconductor package technology, there have been developed various kinds of package structures for semiconductor devices. To form a semiconductor device package structure, a semiconductor component such as an integrated circuit is typically mounted to and electrically connected with a package substrate or a lead frame and then encapsulated by an encapsulant. In BGA semiconductor packaging, a semiconductor component is mounted to and electrically connected to one side of a package substrate. The other side of the package substrate has an array solder balls formed through a self-alignment technology, by which electrical connection can be made to external circuitry.
Although such a package structure enables a higher pin count per unit area, it increases layout difficulty due to a limited substrate surface and prevents the package size from further being reduced, thereby adversely affecting the improvement of electrical performance of the package structure.
In addition, fabrication of chip carriers such as substrates and lead frames, and packaging processes are conventionally conducted by different processing industries, which not only complicates the fabricating process, but also easily leads to incompatible interfaces, thereby making it difficult for customers to make new function designs.
Furthermore, with increasing demand for integrated and miniaturized semiconductor packages, heat produced by a semiconductor chip is accordingly increased. If heat can not be dissipated efficiently, the lifetime and performance of the semiconductor chip can seriously be reduced.
Therefore, an embedded chip package structure is proposed. FIG. 1 shows a conventional embedded chip package structure. As shown in FIG. 1, the package structure comprises a heat spreader 12 with an opening 120; a semiconductor chip 13 with a plurality of electrode pads 130 mounted to the heat spreader 12 and received in the opening 120; a dielectric layer 14 formed on the heat spreader 12 and the semiconductor chip 13; and a circuit layer 15 formed on the dielectric layer 14, the circuit layer 15 being electrically connected to the electrode pads 130 of the semiconductor chip 13 through a plurality of conductive blind vias 150 formed inside the dielectric layer 14.
Since there exists a big difference between CTEs (Coefficient of Thermal Expansion) of the heat spreader 12 and the dielectric layer 14, different thermal stresses generated while temperature changes in fabricating processes such as substrate baking and thermal cycle processing can lead to warpage of the package structure, and even lead to layer delamination and chip crack. To overcome these drawbacks, the thickness of the heat spreader has to be increased to balance the thermal stress resulted from temperature change. However, such a method increases the volume of the package structure and also increases the fabrication cost.
Moreover, chips embedded in the above package structure are generally of same size without constructing a multi-function module. If different sizes of chips are embedded in a substrate, since electrical connecting surfaces of different chips are difficult to be flush with each other, it often leads to an uneven surface of the dielectric layer, which thus adversely affects subsequent fine circuit process.
Accordingly, there exists a strong need in the art for an embedded chip package structure to solve the drawbacks of the above-described conventional technology.